1. Field
Exemplary embodiments of the present invention relate to a semiconductor memory device and, more particularly, to a semiconductor memory device correcting the duty ratio of an internal clock depending on an operation mode and an operation method thereof.
2. Description of the Related Art
With the expanding mobile market, there is a constant demand for miniaturized mobile electronic devices that operate on the limited capacity of a battery. Semiconductor devices used in mobile electronic devices are developed to have high performance while using low power. Therefore, reducing the current consumption in static and dynamic states is an important subject of development in semiconductor memory device of mobile electronic devices.
FIG. 1 is a block diagram illustrating the layout of a typical semiconductor memory device. A semiconductor memory device 100 having an edge pad structure is shown as an example.
Referring to FIG. 1, the semiconductor memory device 100 may include a cell array block 110 and a peripheral circuit block 120 and 130. The cell array block 110 may include a plurality of cell arrays disposed in the center of the semiconductor memory device 100 (i.e. a memory chip). The peripheral circuit block may include first and second peripheral circuit blocks 120 and 130 respectively disposed at the top and bottom of the cell array block 110. When the first peripheral circuit block 120 includes a command/address input pad 140 and a clock input pad 150, the second peripheral circuit block 130 may include a data input/output pad 160.
The semiconductor memory device 100 having the structure described above may operate in synchronization with a clock signal. That is, the semiconductor memory device 100 may exchange data with external devices in response to the clock signal. The clock signal and the data are transmitted through the dock input pad 150 and the data input/output pad 160, i.e., edge pads. In the edge pad structure of the semiconductor memory device 100, however, the clock input pad 150 is disposed a long distance from the data input/output pad 160 and relative circuits since they are disposed at both edges, respectively. The clock signal is to be transmitted through a long transmission path to be used for inputting/outputting the data (Referring to an arrow shown in FIG. 1).
The farther the clock signal is transmitted, the more the dock signal is delayed. A delayed clock signal may influence the characteristics of data outputted from semiconductor memory devices. As semiconductor memory devices operate at high speed and use high frequency clock signals, the influence of delayed clock signals increases. Especially in semiconductor memory devices used in mobile systems supplied with limited power, the operating current may increase and deteriorate operating properties when a correction circuit is employed to correct such clock signals.